Prior art multi-processor computing systems have typically used a “front side bus” between its one or more processors and its memory controller. FIG. 1 shows a traditional multi-processor prior art computing system. According to the depiction of FIG. 1, the front side bus 105 is a “shared medium” component in which electrical signals passed between any processor and any other processor and/or the memory controller 103 are carried over the same electrical wiring.
The front side bus 105 becomes a bottleneck, particularly for multi-processor systems, because there tends to be heavy communication over the front side bus 105 (through small communicative sessions called “transactions”) between the processors 101_1 through 101_4 and the memory controller 103. In order to improve the performance of multi-processor systems, a new architecture has emerged (which may be referred to as “link based”) in which the front side bus is replaced with a network having point-to-point links between the processors and memory controller.
FIG. 2 shows an example. Here, note that the system nodes 201_1 through 201_4 and memory controller 203 (“home agent”) are communicatively coupled by a network 205 having point-to-point links between these components. For ease of drawing the point-to-point links are depicted as being bi-directional. Typically, however, these bi-directional point-to-point links are actually implemented with a pair of uni-directional point-to-point links directed in opposite directions with respect to one another. According to the architecture of FIG. 2, a “system node” is a unit containing one or more processing cores (e.g., one or more units of logic circuitry that executes program code). A “system node” may also have associated cache 202_1 through 202_4 for its respective processing cores.
Of interest in these systems are the transactions that occur over the network 205 between the system nodes 201_1 through 201_4 and memory controller 203 (e.g., to effect coherent caching and shared access to the system memory for data and/or instructions). Observing transactions for test and/or de-bug purposes in a system whose processing cores are interconnected through a mesh of point-to-point links (as depicted in FIG. 2) is significantly more difficult to accomplish as compared to systems whose processors are interconnected by a front side bus (as depicted in FIG. 1).
As just one perspective, in a front side bus system, each processor in the system can sense all activity on the bus initiated by the other processors. By contrast, a processing core in a point-to-point system has limited visibility into the activities of the processing cores of the other system nodes (e.g., system node 201_1 cannot detect the communications that exist on the point-to-point link that connects system node 201_2 and memory controller 203). As a consequence, a single transaction may involve the passing of multiple messages between different components on different point-to-point links. For instance, in order to issue a request from system node 201_1 for an item of data, separate requests for the data may be sent from system 201_1 to each of processors 201_2 through 201_4 and memory controller 203 along their respective point-to-point links.
In this sense, the transaction in the point-to-point link system is more difficult to detect and/or observe as compared to a corresponding transaction in a front side bus system because the transaction is developing over a plurality of communication structures (specifically, over a plurality of point-to-point links) as opposed to a single communication structure (specifically, a front side bus).